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Author: | Wang Qianggang[1] Lei Chao[2] Li Yong[2] Zhou Niancheng[1] Zhu Jizhong[3] |
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电工技术学报 ISTIC EI SCI PKU CSSCI |
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Transactions of China Electrotechnical Society ISTIC EI SCI PKU CSSCI |
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2018, 33(5) |
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TM71 |
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受端电网
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Receiving power system dynamic reactive power optimization infeasible voltage-violated bus infeasible time periods |
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2018年4月9日 |
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国家自然科学基金项目资助 |