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一种低功耗亚阈值全MOS管基准电压源的设计

一种低功耗亚阈值全MOS管基准电压源的设计

Design of a low power sub-threshold all MOSFET voltage reference

Design of a low power sub-threshold all MOSFET voltage reference

doi:
10.14106/j.cnki.1001-2028.2016.05.007
摘要:
分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为线性区MOS管提供偏压以进一步降低功耗。基于SMIC 0.18μm CMOS工艺设计电路。仿真结果表明此电路在1.8 V电源电压下,–50~+150℃的温度系数为22.6×10–6/℃,基准电压源输出电压约为992 mV,25℃时静态电流为327.3 nA,电路总静态功耗为0.59μW,10 kHz时的电源抑制比为–25.36 dB。
Abstract:
A low power voltage reference circuit with all MOSFET structure was presented based on the different current characteristics of the MOSFET sub-threshold region, linear region and saturated region. The MOSFET working in linear region was designed to replace the ordinary resistance, to realize the all MOSFET characteristic, at the same time, the circuit layout area was effectively reduced. Besides, the output reference voltage was used as the bias of the MOSFET to further reduce power consumption. The circuit was designed with SMIC 0.18μm CMOStechnology. Results denote that the temperature coefficient is 22.6×10–6/℃ in –50-+150℃ with the power supply of 1.8 V, and the output voltage of the voltage reference circuit is 992 mV. The static current at 25℃ is 327.3 nA, and the power consumption is 0.59μW. Besides, the power supply rejection ratio is –25.36 dB at 10 kHz.
作者 张涛 陈远龙 王影 曾敬源 张国俊
Author: ZHANG Tao CHEN Yuanlong WANG Ying ZENG Jingyuan ZHANG Guojun
作者单位 电子科技大学 电子薄膜与集成器件国家重点实验室,四川 成都,610054
期 刊: 电子元件与材料 ISTIC EI SCI PKU CSSCI
年,卷(期) 2016, 35(5)
分类号 TN432
关键词: 基准电压源 知识脉络 全MOSFET 知识脉络 亚阈值 知识脉络 低功耗 知识脉络 低温度系数 知识脉络 线性区 知识脉络
Keywords: voltage reference all MOSFET sub-threshold low power low temperature coefficient linear region
机标分类号 TN4 TN7
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